Marvell Technology

Marvell will present at IEEE International Test Conference India 2026, now in its 10th edition and one of the semiconductor industry's leading forums for design verification, test, and silicon debug.

Senior Principal Engineer Sreekanth G Pai and Senior Engineer Raseena K A will present on mission-mode scan dump using IJTAG and TAP customization, addressing one of the more demanding challenges in modern SoC development: maintaining robust observability and debuggability during mission-mode operation at scale.

As SoC complexity continues to grow, the ability to efficiently access internal silicon states with minimal design impact is becoming a critical capability. Their session offers practical insight into IJTAG-based architectures, scan data extraction, and verification strategies for advanced semiconductor designs.

Learn more: https://mrvl.co/3QIwbHy

As AI clusters scale and Mixture of Experts architectures grow in complexity, the diversity of interconnect standards is expanding rapidly. UALink, ESUN, NVLink, and others are creating what Preet Virk calls a "chiplet smorgasbord," a proliferation of die-to-die interfaces, protocols, physical layers, and external interfaces that demands a fundamentally different design approach.

Preet will deliver a keynote at the EE Times Chiplet Summit exploring how system-level co-design across compute, switches, and memory, anchored by architectural control of SerDes, optics, advanced packaging, and test IP, is essential to managing this complexity at scale.

Register for this virtual event here: https://mrvl.co/4uLxLqb