QBayLogic

Everyone at QBayLogic is really excited by the Lion core that was just announced by Standard Semiconductor: https://github.com/standardsemiconductor/lion
It's a pipelined RISCV core written in Clash, formally verified using Clair Xen's awesome riscv-formal suite.

standardsemiconductor/lion Where Lions Roam: RISC-V on the VELDT. Contribute to standardsemiconductor/lion development by creating an account on GitHub.

"Programming an FPGA by simply describing the functionality of the application.” Intrigued? Then join our free online seminar at the FHI D&E event, November 18 11:30am UTC+1:

How to program an FPGA | D&E Event FPGAs are on the rise as they are faster and more energy efficient than normal CPUs. Applications can be found in widely varying fields, such as big data,