VLSI - PD

1. Insertion Delay
✅ Definition
Insertion delay is the time taken for the clock signal to travel from the clock source (root) to a particular register (sink).

🧠 Key idea
It measures how long the clock takes to reach a specific endpoint.

Formula
Insertion Delay = Time(clk arrives at flip-flop) − Time(clk leaves source)

includes:
Buffers
Clock tree routing

⚠️ Insertion Delay
Not dangerous if balanced
Problem if:
Too high → affects clock period
Uneven → creates skew

Fixing Insertion Delay
Clock Tree Synthesis (CTS optimisation)
Buffer insertion
Reduce clock path length
Use higher metal layers
Shield clock nets
👉 Tools:
CTS engines (ICC2, Innovus)

2. Latency
✅ Definition
Latency refers to the overall delay of the clock network, and it can be:
Source Latency → outside the chip (PLL, clock generation)
Network Latency → inside the chip (clock tree)

🧠 Key idea
It represents the total delay from clock generation to reaching the registers.

Formula
Latency = Source Latency + Network Latency

⚠️Latency
Context dependent
Data latency ↑ → setup violation
Not inherently dangerous

Fixing Latency
Data Path:
Logic optimization
Pipelining
Gate sizing
Retiming
Clock Path:
CTS improvements

3. Skew
Skew (Clock Difference)
Difference in clock arrival time between two flip-flops
Types:
Positive skew: Capture clock arrives later → helps setup
Negative skew: Capture clock arrives earlier → hurts setup

Formula
Skew = FF1 − FF2

⚠️Most Dangerous → Skew
👉 Why?
Directly affects: Setup violations, Hold violations
Even small skew → large timing failure

Fixing Skew (Very Important)
Balanced clock tree
H-tree / X-tree structures
Useful skew optimization
Buffer tuning
Clock mesh (advanced nodes)
👉 Key concept:
“Balance clock arrival across all FFs”

Bounds in VLSI Physical Design
In VLSI Physical Design, Bounds are used to control placement of cells within a specific region of the chip. They are very important for floorplanning, congestion control, and timing optimization.

🔹 What are Bounds?
👉 A bound is a logical constraint region that restricts where certain cells can be placed.
✅ It defines a rectangular area
✅ You assign specific instances (cells) to that area
✅ The tool tries to keep those cells inside the bound

🔹 Why Bounds are Used?
1. Timing Optimization
⏺️ Keep related cells close → reduces wirelength → improves timing
2. Congestion Control
⏺️ Spread cells across regions to avoid routing congestion
3. Hierarchical Design
⏺️ Maintain block-level grouping
4. Physical Constraints
⏺️ Keep interface logic near macros or IO pins

🔹 Types of Bounds
1. Soft Bound
👉 Tool tries to keep cells inside, but can violate if needed
▪️ Flexible
▪️ Used when timing is more important than strict placement
2. Hard Bound
👉 Tool strictly enforces placement inside the region
▪️ No movement outside allowed
▪️ Used for strict floorplan requirements
3. Partial Bound
👉 Controls density inside a region
▪️ Limits how much area can be occupied
▪️ Example: only 70% utilization allowed

in Innovus :
createBound -type soft B1 100 200 500 400
createBound -type hard B2 600 100 900 500
createBound -type partial -density 0.7 B3 100 600 500 900
addInstToBound B1 [get_cells U1 U2 U3]

👉 Interview Tip:
Bounds = guidance + grouping
Regions = strict placement control