TTTC Seminar on VLSI Testing and Testability

TTTC Seminar on VLSI Testing and Testability

Share

19/06/2024
Photos from TTTC Seminar on VLSI Testing and Testability's post 15/11/2023

Dear Sir/madam,

School of Electronics Engineering (SENSE), VIT, Vellore organizing a two-week National workshop (online) on "System On Chip Design using Open-power" from November 20, 2023 to December 2, 2023 supported by IBM, OpenPower and Object Automation.

Eminent speakers from Industry, National Laboratories and IITs will handle the session.

You are cordially invited to register and attend the workshop. Virtual lab access will be provided to all the participants.

Registration fee: Rs 2000/-
For registration, https://events.vit.ac.in/
on or before 18.11.2023

Want your school to be the top-listed School/college in Vellore?
Click here to claim your Sponsored Listing.

Website

Address

Vellore
632014